搜索资源列表
fir_verilog_matlab
- 本设计是基于FPGA的一个FIR低通滤波器设计，要求使用Verilog语言编写滤波器模块，通过编译和综合，并通过Matlab和modelsim联合仿真验证设计结果。-This design is a FIR low-pass filter design based on FPGA, use Verilog to program filter module, and joint simulation by Matlab and modelsim to validate the design re
20140431
- 这是关于fallow滤波器的设计，设计平台为FPGA，使用verilog语言，希望对使用者能用帮助-This is the fallow filter design, design platform FPGA, using verilog language, and I hope to be able to help users
farrow
- farrow滤波器verilog代码，完成分数倍的抽取-farrow filter verilog code to complete the fractional extraction
code
- 用Verilog写的采用LSM算法的自适应性FIR滤波器，有testbench和主体代码，亲测可用-Written using Verilog LSM algorithm using adaptive FIR filters, and the body has testbench code, pro-test available
FIR
- 用Verilog HDL实现FIR滤波器的功能，文件包括Verilog HDL的源代码。-Using Verilog HDL realize the FIR filter function, the file includes Verilog HDL source code.
fir16.v
- 16阶FIR滤波器设计的verilog代码-Verilog 16-order FIR filter
fir48
- 48阶FIR滤波器的verilog，包含测试文件-48-order FIR filter verilog, including test paper
shape
- 基于FPGA的成型滤波器的代码，里面内附激励文件，使用verilog编写-FPGA-based shaping filter code, which included incentives files using verilog write
IFFT
- 一个IFFT滤波器的verilog源代码，用于滤波器设计参考-An IFFT filter verilog source code for filter design reference
Middlefilter
- 基于FPGA的中指滤波器，使用verilog语言实现，仿真结果正常。-FPGA-based middle filter using verilog language, simulation results properly.
filter
- 数字滤波器的verilog语言程序，为双精度的滤波器，可以实现10k低通滤波-verilog filter
20140825
- FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code
FIR
- FPGA设计在设计过程中使用ISE软件自带的IP核时，消耗资源太大的时候，需要自己编写滤波器的源代码，这里给出我们常用的串行FIR核的verilog语言代码设计文件，并通过作者时序仿真验证，并用于实际的项目中。-The FPGA design in the design process of ISE software used to own the IP core, consume resources is too big, need to write your own source code
1
- verilog编写的11阶FIR数字滤波器-The 11 order FIR digital filter Verilog prepared!!!!!!!!!!!!!!!!!!!!!
8fir
- 这是一个verilog语言描述的8阶fir滤波器-8firFILTERdesign
high-pass-filter-design
- 基于verilog的高通fir数字滤波器设计-Verilog fir digital high-pass filter design based on
cic-dicemator
- 该文件包含数字抽取滤波器cic的verilog代码，经测试可用，且简介，消耗硬件资源较少。-This file contains digital sampling filter cic verilog code, after testing is available, and the introduction, less consumption of hardware resources.
FIR32
- 基于DA算法的FIR带通滤波器设计，应用于FPGA实现，verilog语言描述-DA algorithm based on FIR bandpass filter design, used in FPGA implementation, verilog language to describe
RLS.v
- 用verilog实现的一个2抽头RLS自适应滤波器的代码-A realization with verilog HDL code of a two-tap RLS adaprive fliter
filter
- 大神写的FIR滤波器，verilog所写，短小精悍，易读懂！-Great God wrote the FIR filter, verilog written, short and pithy, easy to read!